Central processing unit
6
68k
A
Advanced Load Address Table
Architectural state
Arithmetic logic unit
B
Barrel processor
Berkeley RISC
Brainiac CPU
C
CPU bound
CPU cache
CPU card
CPU core voltage
CPU design
CPU locking
CPU modes
CPU power dissipation
Cache
Cache coherency
Complex instruction set computer
Computer architecture
Control register
Computer cooling
Cycle stealing
D
Data path unit
Double fault
E
Exec Shield
Execution unit
H
HIP (architecture)
Hardware performance counter
History of general purpose CPUs
I
Instruction set
Instruction unit
L
Little man computer
M
MESI protocol
Micro-operation
Microarchitecture
Microcode
Microcontroller
Minimal instruction set computer
Multithreading (computer hardware)
N
NX bit
Notable CPU architectures
P
Page size
Parity flag
Processor register
R
Reduced instruction set computer
Reset vector
Ring (computer security)
S
Stride scheduling
T
Teraflops Research Chip
Translation Lookaside Buffer
W
Wait state
Z
Zero Instruction Set Computer
Fonte: Wikipedia
6
68k
A
Advanced Load Address Table
Architectural state
Arithmetic logic unit
B
Barrel processor
Berkeley RISC
Brainiac CPU
C
CPU bound
CPU cache
CPU card
CPU core voltage
CPU design
CPU locking
CPU modes
CPU power dissipation
Cache
Cache coherency
Complex instruction set computer
Computer architecture
Control register
Computer cooling
Cycle stealing
D
Data path unit
Double fault
E
Exec Shield
Execution unit
H
HIP (architecture)
Hardware performance counter
History of general purpose CPUs
I
Instruction set
Instruction unit
L
Little man computer
M
MESI protocol
Micro-operation
Microarchitecture
Microcode
Microcontroller
Minimal instruction set computer
Multithreading (computer hardware)
N
NX bit
Notable CPU architectures
P
Page size
Parity flag
Processor register
R
Reduced instruction set computer
Reset vector
Ring (computer security)
S
Stride scheduling
T
Teraflops Research Chip
Translation Lookaside Buffer
W
Wait state
Z
Zero Instruction Set Computer
Fonte: Wikipedia